Large Capacitance With Small Volume and WeightTechnology #ua05-068
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- Olgierd Palusinski Professor (Retired), Electrical & Computer Engineering
- Grzegorz Zareba Senior Engineer, Steward Observatory
- Jaeheon Lee
- Kenneth Bartley Electrical & Computer Engineering
- Zuzanna Siwy Assistant Professor, Physics & Astronomy
- Managed By
- Robert Sleeper Licensing Manager (520) 626-4604
Background: This invention proposes a unique, relatively simple, and controllable manufacturing process that yields a compact 3D structure with a very high capacitance to volume ratio- more than 10,000 times larger than a conventional parallel plate capacitor. This development makes way for a device with large capacitance, but very small size that will help catalyze the miniaturization of electronics.
Invention: The unique feature of this invention is the manufacturing process, which uses commercially available or customized dielectric membrane templates with nano-pores to increase the surface area of the conducting materials allowing for more capacitance per unit area than a parallel plate capacitor could ever hope to achieve. This process will most likely impact integrated circuits and portable electronics, but due to its small size and unique features it may find its way into new applications not conceived of today. Digitated capacitors have been fabricated using commercial filters such as polycarbonate and aluminum oxide membranes. 10µm, 20µm, and 60µm thick membranes were explored with pore diameter ranging from 15nm to 1µm and density of 106 to 1010 pores/cm2. Nanopores on the membranes were filled by electrodeposition with copper to form the digitated nano structure. The digitated device fabricated to date showed 10-100mF/cm3 or 1-10mF/gram of capacitance density which is much superior to the commercial parallel plate capacitors. Conducting polymer can also be deposited in nanopores resulting in storing more charges with less weight thus yielding a further increase in capacitance density. We also have technology for building custom templates, which is useful in fabrication of devices with special features. A capacitor of 4F can be built using a 20cm2 barium titanate template of 100µm thickness. Connecting nano structured capacitors in parallel will lead to capacitor packs with significant storage capacity (hundreds of Farads) for high-energy consuming applications from portable devices to pulse power demanding vehicles. We have developed technology for building interdigitated devices with even greater storage capabilities.
* Large capacitance, very small physical volume and weight
* Very high capacitance to volume ratio: 10,000x that of commercial electrostatic capacitors
* Relatively simple and controllable manufacturing process
* Various membrane and inclusion materials can be used to modify device characteristics
* Nano-structure devices act as current sources and capacitors
* Integrated Circuits (IC)
* Small-scale & portable electronics
* Stand-alone sensor network device
Stage of Development: Work is ongoing.
Lead Inventors: Prof. Olgierd A. Palusinski, Grzegorz Zareba, Ph.D., Jaeheon Lee, Ph.D., Kenneth L. Bartley, and Prof. Zuzanna S. Siwy
Status: US patent 8,835,046
Refer to Case No. UA05-068