Invention:
This invention leverages high-resolution lithography and etching to develop nanopatterned gating layers for modifying electronic, optical, and magnetic properties in 2D materials, specifically monolayer semiconductors. This technology integrates nano-scale patterned graphene gates into a two-dimensional semiconductor heterostructure, allowing for precise control over the semiconductor’s charge configuration. By using a 2D-periodic lattice with customizable spacing and hole diameters, this method enables the spatial tuning of correlated electronic states. The patterned gates provide a flexible and tunable potential landscape, resulting in enhanced optical, electronic, and magnetic properties.
Background:
2D materials, such as monolayer semiconductors, exhibit unique properties due to their atomic-scale thickness and are highly sensitive to external fields and gating techniques. Current technologies that manipulate 2D semiconductors face limitations due to their reliance on external magnetic fields and extreme conditions, making them costly and difficult to scale for practical applications. Moreover, existing gating techniques offer limited flexibility because they depend on the intrinsic crystal lattice of the materials, which cannot be easily modified. The disclosed technology overcomes these issues by introducing a nano-patterned graphene gate, which allows for customizable tuning of charge configurations without the need for extreme environmental conditions. This makes the technology cheaper, more efficient, and easier to implement in a variety of applications, including optoelectronics, sensors, and quantum devices.
Applications:
- Transistors
- Quantum computing
- Optoelectronics
- Nanoscale magnetics
- Memory devices
Advantages:
- Precise tuning
- Multi-property control
- Energy efficiency
- Scalability
