Invention:
This technology is a method of finding the ideal hardware choices to execute a given quantum algorithm, by explicitly treating compilation within the framework of quantum error-correcting codes and logical operator equivalence in the special unitary group. Quantum hardware is noisy, and certain hardware combinations can be even more so. This technology introduces a systematic method to develop distinct, error-corrected circuits that are logically equivalent to circuits with connectivity or compilation problems.
Background:
Typically, connectivity problems in quantum hardware are addressed by incorporating qubit swap gates, which are expensive. This technology offers a different approach to reducing compilation errors by simply replacing poor-connectivity quantum circuits with logically equivalent circuits that adhere to hardware connectivity.
Applications:
- Quantum computing
- Quantum hardware
- Error-corrected quantum circuits
Advantages:
- Reduces cost
- Systematic technique
- Improving feasibility on constrained quantum hardware
