Relaxed Tolerance Adiabatic Coupler for Optical Interconnects

Case ID:

Researchers at the University of Arizona have designed an architecture for photonic integrated circuits (PICs) using a waveguide design that reduces the size of the interconnections and overcomes the mode size mismatch. The design also relaxes alignment tolerances and lower polarization dependence to allow for very fast manufacturing of the PIC interconnections.


An important problem in optical packaging involves the optical interconnection of photonic integrated circuits (PICs) for chip-chip connections and the connection of such circuits to the external world. PICs use waveguide components for the transformation of electrical signals to optical signals and vice versa.  Existing wire bonding techniques that have been successfully applied to electrical connections in electronic integrated circuits cannot be easily extended to optical connection in a photonic integrated circuit.  Even optical-to-optical interconnects to fiber optics suffer from mode size mismatch, which greatly reduces the coupling efficiencies.



  • Higher coupling efficiency and lower signal losses
  • Relaxed alignment tolerances
  • Faster manufacturing
  • Short distance for inter-chip and optical printed circuit board connections


  • Telecommunications
  • Optical packaging
Patent Information:
Contact For More Information:
Richard Weite
Senior Licensing Manager, College of Optical Sciences
The University of Arizona
Lead Inventor(s):
Erfan Fard
Robert Norwood
Thomas Koch
Stanley Pau